High power consumption can lead to high heat dissipation as well as to short battery life. Modern systems are required to operate for relatively long periods before being recharged.
Various techniques were developed in order to reduce the power consumption of modern systems, some being described in the following U.S. patents and patent applications, all being incorporated herein by reference: U.S. Pat. No. 6,115,823 of Velasco et al., titled “System and method for task performance based dynamic distributed power management in a computer system and design method therefore”; U.S. Pat. No. 6,807,227 of Chein, titled “Method of reconfiguration of radio parameters for power aware and adaptive communications”; U.S. patent application publication number 2004/0225901 of Bear et al., titled “Method and system for auxiliary processing of information for a computing system”; U.S. patent application publication number 2003/0061526 of Hashimoto, titled “Computer system and power saving control method therefore”; U.S. Pat. No. 6,901,521 of Chauvel et al., U.S. Pat. No. 5,712,826 of Wong et al., titled “Apparatus and method for embedding dynamic state machines in a static environment”; U.S. Pat. No. 6,584,571 of Fung, titled “system and method of computer operating mode clock control for power consumption reduction”, U.S. Pat. No. 6,079,025 of Fung titled “system and method of computer operating mode control for power consumption reduction”, and U.S. patent application publication number 2002/0042887 of Chauvel et al., titled “Dynamic hardware configuration for energy management systems using task attributes”.
A very popular power reduction technique is known as dynamic voltage scaling (DVS) or alternatively is known as dynamic voltage and frequency scaling (DVFS) and includes altering the voltage that is supplied to an integrated circuit as well as altering the frequency of a clock signal that is provided to the integrated circuit in response to the load of the integrated circuit. Higher voltage levels are associated with higher operating frequencies and higher computational load but are also associated with higher energy consumption.
There is a need to provide an efficient manner to decrease and increase voltage level and clock signal frequency provided to a system.